1. Field of the Invention
The present invention relates to a digital satellite broadcasting receiver for receiving, demodulating and processing broadcasting signals from a satellite, for example, to output data. More specifically, the present invention relates to a digital satellite broadcasting receiver not susceptible to noise and almost free from the possibility of losing carrier lock in a PLL circuit for carrier recovery at the time of centering.
2. Description of the Background Art
In a digital satellite broadcasting receiver, a channel of the satellite broadcasting signal is selected by a channel selecting circuit, the signal is converted to an IF (Intermediate Frequency) signal and subjected to IQ demodulation to be an analog IQ signal of pseudo baseband. The analog IQ signal is further converted to a digital signal and demodulated at a QPSK (Quadrature Phase Shift Keying) demodulating section, subjected to a prescribed signal processing, and output as data.
The QPSK demodulating section includes a carrier recovery section, which carrier recovery section detects any frequency error and an optimal phase. The channel selecting circuit has a PLL (Phase Locked Loop) and when a frequency divider in the PLL is provided with data for frequency division from a control circuit, the channel selecting circuit can select channels and change frequency stepwise.
The QPSK demodulating section provides demodulated data. However, even at this time point, there still remains carrier offset. Therefore, centering of the satellite broadcasting receiver is necessary to minimize the offset.
Conventionally, centering is performed in the following manner. FIG 8 is a flow chart of the control circuit at time of centering in a conventional digital satellite broadcast receiver. Referring to FIG. 8, a carrier offset signal is read from the QPSK demodulating section (S5). Frequency of the PLL of the channel selecting circuit is changed one step by one stop in a direction of reducing the amount of carrier offset (S10), and when it is detected that the amount of carrier offset attains to be smaller than the step width of the channel selecting PLL (S15), centering operation is completed (S20). This is because further correction is not possible when the amount of carrier offset is smaller than the stop width of the channel selecting PLL.
Such a conventional technique has quick response and is strong against shock noise when the loop bandwidth of the channel selecting PLL is wide. However, when the channel selecting frequency of the channel selecting PLL is shifted one step by one step at the time of centering, the carrier recovery PLL of the QPSK demodulating section in the succeeding stage cannot follow the channel selecting PLL, so that carrier lock is lost. Conversely, when the loop bandwidth of the carrier recovery PLL of the succeeding stage is made wider, there is less possibility that the carrier recovery PLL fails to follow the channel selecting PLL. However, it is more likely that characteristics against signal noise are deteriorated in normal reception, resulting in inferior bit error rate.
Therefore, an object of the present invention is to provide a digital satellite broadcasting receiver capable of preventing increase in noise in normal receiving state while maintaining carrier lock of the carrier recovery PLL at the time of centering, and to provide the method thereof.
Another object of the present invention is to provide a digital satellite broadcasting receiver capable of preventing increase in noise in normal receiving state while allowing a carrier recovery PLL to follow an operation of a channel selecting PLL at the time of centering, and to provide the method thereof.
Another object of the present invention is to provide a digital satellite broadcasting receiver in which response of a channel selecting PLL is made slow enough to allow a carrier recovery PLL to follow at the time of centering and the response for channel selection is made quick in normal receiving state, and to provide the method thereof.
The digital satellite broadcasting receiver in accordance with the present invention includes: a channel selecting circuit having a first PLL circuit; a carrier recovery circuit receiving an output from the channel selecting circuit and having a second PLL circuit; a switching circuit for switching loop bandwidth of the first PLL circuit; and a control circuit for controlling the switching circuit such that the loop bandwidth of the first PLL circuit is made narrower at the time of centering than in the loop bandwidth a normal receiving state and/or at a time of channel switching time of centering.
In the digital satellite broadcasting receiver structured as described above, the bandwidth of the first PLL circuit for channel selection is wide at the time of channel selection and in the normal receiving state, so that response for channel selection is quick and therefore the receiver is less susceptible to shock noise. At the time of centering, the bandwidth of the first PLL circuit for channel selection is made narrower, so that the second PLL circuit of the carrier recovery circuit easily follows the operation of the first PLL circuit, and therefore it is less likely that the carrier lock is lost.
Preferably, the channel selecting circuit has a first function for tuning, based on an applied control signal, with a channel selecting frequency designated by the control signal, and a second function of changing one step by one step an oscillation frequency of the first PLL circuit. The channel selecting circuit further controls the switching circuit when it performs the second function such that the loop bandwidth of the first PLL circuit is made narrower than when it performs the first function.
According to another aspect of the present invention, the digital satellite broadcasting receiver includes: a channel selecting circuit having a first PLL circuit; a carrier recovery circuit receiving an output from the channel selecting circuit and having a second PLL circuit; a switching circuit for switching loop bandwidth of the second PLL circuit; and a control circuit for controlling the switching circuit such that the loop bandwidth of the second PLL circuit is made wider than in a normal receiving state and at the time of channel switching, at the time of centering.
The method of centering in a digital satellite broadcasting receiver in accordance with a still further aspect of the present invention includes the steps of: narrowing loop bandwidth of a PLL circuit for channel selection included in a channel selecting circuit; in the PLL circuit of which loop bandwidth is made narrower, changing a synchronizing frequency of the PLL circuit so that an amount of carrier offset obtained from a demodulated signal is minimized; and after the amount of carrier offset obtained from the demodulated signal is minimized, widening the loop bandwidth of the PLL circuit.
The method of centering in a digital satellite broadcasting receiver in accordance with an additional aspect of the present invention includes the steps of: widening loop bandwidth of a carrier recovery PLL circuit of the digital satellite broadcasting receiver; thereafter, in a PLL circuit included in a channel selecting circuit of the digital satellite broadcasting receiver, changing a synchronizing frequency so that an amount of carrier offset obtained from a demodulated signal is minimized; and after the amount of carrier offset obtained from the demodulated signal is minimized, narrowing the loop bandwidth of the carrier recovery PLL circuit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings, wherein like elements are represented by like reference numerals, which are given by way of illustration only, and thus are not limitative of the present invention, and wherein: